PLLs are commonly used in synthesizer subsystems. Turning to FIG. 1 of the drawings, an example of a conventional PLL 100 using continuous calibration can be seen. The PLL 100 is generally comprised of a phase/frequency detector (PFD) 202, charge pump 204, loop filter 206, a dual gain voltage controlled oscillator (VCO) 102, divider 220, amplifier 218, and calibration capacitor CCT. In this configuration, there are two separate analog loops, a low bandwidth loop (formed with the error amplifier 218 and VCO 102) and a high bandwidth loop (formed with divider 220 and VCO 102) so that the low bandwidth loop can apply a coarse tuning voltage VC to the VCO 102 and that the high bandwidth loop can apply a fine tuning voltage VF to VCO 102.
In operation, the high bandwidth loop operates as a conventional single path PLL, providing a low tuning gain characteristic for VCO 102 with the application of the fine tuning voltage VF to VCO 102, whereas the low bandwidth loop allows for the provision of a wide frequency tuning range characteristic. In particular with the low bandwidth loop, transconductance error amplifier 218 amplifies the difference between the fine tuning voltage VF (output from loop filter 206) and reference voltage REF, and this difference is applied as a current to capacitor CCT so as to generate coarse tuning voltage VC, which is applied to VCO 102 for the wide tuning bandwidth of VCO 102. The low frequency loop will coarsely tune the wideband VCO to within a range where the high bandwidth loop becomes operational. This is accomplished by providing continuous (but low frequency) correction to the VCO 102. Because the low bandwidth loop tracks low frequency changes in the input signal, this loop will have little direct influence on the spur level and wide band phase noise performance of the PLL 100.
The high bandwidth loop does not operate until the VCO 102 is tuned to a frequency that falls within the fine frequency input tuning range of VCO 102, where the fine tuning gain of VCO 102 becomes non zero. The high bandwidth loop is generally responsible for setting the generally relevant noise characteristics. In the conventional single loop PLL the tradeoff between tuning range and noise performance is tightly coupled. The use of two loops effectively decouples this trade-off, allowing PLL 100 to offer better performance over other conventional single path PLLs.
A drawback of this configuration, however, is the slow settling time of PLL 100. Generally, the slow settling time can be attributed to the low bandwidth, coarse tuning loop. Another drawback is the size of capacitor CCT, which is often very large in order to suppress the noise of amplifier 218. Due to these drawbacks, there are some systems where PLL 100 is undesirable. Therefore, there is a need for a PLL with improved performance characteristics.
Some other conventional circuits are: Wu et al., “A 4.2 GHz PLL Frequency Synthesizer with an Adaptively Tuned Coarse Loop”, IEEE 2007 Custom Intergrated Circuits Conference, pp. 547-550; Nonis et al., “Modeling, Design and Characterization of a New Low-Jitter Analog Dual Tuning LC-VCO PLL Architecture”, IEEE J. OF Solid-State Circuits, Vol. 40, No. 6, June 2005, pp. 1303-1309; Perrott et al., “A 2.5-Gb/s Multi-Rate 0.25-μm CMOS Clock and Data Recovery Circuit Utilizing a Hybrid Analog/Digital Loop Filter and All-Digital Referenceless Frequency Acquisition”, IEEE J. OF Solid-State Circuits, Vol. 41, No. 12, December 2006, pp. 2930-2944; U.S. Pat. No. 6,658,748; U.S. Pat. No. 6,952,124; U.S. Pat. No. 7,015,763; U.S. Pat. No. 7,133,485; U.S. Pat. No. 7,301,407; U.S. Pat. No. 7,385,452; U.S. Pat. Pre-Grant Publ. No. 2002/0008593; U.S. Patent Pre-Grant Publ. No. 2003/0141936; U.S. Patent Pre-Grant Publ. No. 2005/0212609; U.S. Patent Pre-Grant Publ. No. 2005/0212614; U.S. Patent Pre-Grant Publ. No. 2007/0057736; and datasheet for Texas Instruments Incorporated's CDCE421.